The present invention relates to the distribution of clock signals to various points on a semiconductor device, such as a large scale integrated (LSI) circuit, and, more particularly, the present invention relates to the use of active feedback and correction of clock skew on a global level.
A system clock signal is often used by digital circuitry, such as digital circuitry implemented using a LSI circuit, to synchronously execute certain logic functions. For example, ultra-deep sub-micron (UDSM) microprocessors employ digital circuitry that use system clock signals to synchronously execute logic functions. These microprocessors operate at system clock frequencies of 1 GHz and higher. The system clock signal of a given LSI circuit is often split into many paths to service many different portions of the digital circuitry. Ideally, the system clock signals at different portions of the digital circuitry exhibit exactly the same timing characteristics so that the different portions of the digital circuitry operate in exact synchronization. In practice, however, the system clock signals at various points throughout the digital circuitry exhibit differing timing characteristics, such as differing rising and/or falling edges (i.e., transitions), differing duty cycles, and/or differing frequencies. These non-ideal characteristics are often referred to as clock jitter and clock skew.
Clock jitter relates to the inaccuracies inherent in generating the system clock signal. The non-ideal characteristics of the system clock signals due to clock jitter effect all portions of the LSI circuit in the same way, irrespective of how the system clock signals are distributed to those portions of the circuit. Clock skew relates to the inaccuracies introduced into the system clock signals by the distribution technique employed to split the system clock into many paths and deliver the clock signals to different portions of the digital circuit.
Sources of clock skew may be classified as being statically occurring or dynamically occurring. Statically occurring sources of clock skew are caused by the LSI design or manufacturing process irrespective of the operating conditions of the LSI circuit. Dynamically occurring sources of clock skew are caused by the operating conditions of the LSI circuit, which may also be functions of the LSI circuit design or manufacturing process.
Statically occurring sources of clock skew include (i) variations in transistor load capacitance (e.g., gate load capacitance); (ii) RC delay of circuit interconnections (e.g., the asymmetry of wire lengths and widths); (iii) variations and/or asymmetries in cross-coupling capacitance between wires (e.g., inter-wiring capacitance); and (iv) semiconductor process variations (e.g., transistor threshold voltage variations, transistor ON resistance variations, wiring variations, veer, and contact RC variations).
Dynamically occurring sources of clock skew include (i) cross-coupling between wire lengths due to inter-wiring capacitance; (ii) cross-coupling between wire lengths due to inductive coupling; (iii) cross-coupling due to return path current; (iv) temperature variations; and (v) variations in VDD and VSS (e.g., DC operating voltage variations).
Unfortunately, the variations in the timing characteristics of the system clock signals due to clock skew result in undesirable errors in the operation of the digital circuitry of the LSI circuit. The problem is exacerbated as the size (i.e., number of logic gates and corresponding circuit area) increase and/or as the clock signal frequency increases.
Various techniques have been developed and employed to ameliorate the undesirable affects of clock skew. These techniques include (i) utilizing clock bars (i.e., relatively wide bars to carry the system clock to various portions of the LSI circuit); (ii) RC delay balancing (i.e., wiring techniques that focus on wiring geometry to match RC delay characteristics); (iii) utilizing a grid structure in distributing the system clock signal; (iv) utilizing a hierarchical structure in partitioning the LSI circuit into regions; (v) utilizing active feedback in compensating the system clock signal; (vi) utilizing local oscillators in various regions of the LSI circuit and an overall resonance for the LSI circuit; and (vii) utilizing the resonances of wiring loops. For various reasons, these techniques have not been adequately successful in addressing the undesirable problems caused by clock skew.
In accordance with one or more aspects of the present invention, a semiconductor chip includes a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers, each including a delay lock loop (DLL) circuit providing a DDL function and each being operable to produce a respective output clock signal from an associated input clock signal in accordance with the DLL function, the outputs of a subset of the plurality of clock buffers being coupled to respective ones of the plurality of regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the output clock signals of at least two of the regional clock distribution nodes, wherein the DDL circuits of the Nth subset of clock buffers adjust the respective output clock signals in accordance with the respective error signals such that the output clock signals of the regional clock distribution nodes are substantially coincident.
Preferably, the clock buffers are coupled to one another to form a clock distribution tree from a clock source to the clock distribution nodes. The clock distribution tree may be an H-tree.
Preferably, first through Nth level subsets of the plurality of clock buffers define distribution levels of the distribution tree. The respective clock buffers of the first level subset are operable to produce respective first level output clock signals from a source clock signal in accordance with their DLL functions and one of the error signals. Respective groups of clock buffers of the second level subset are operable to produce respective second level output clock signals from the respective first level clock signals in accordance with their DLL functions and respective error signals. Respective groups of clock buffers of the third level subset are operable to produce respective third level output clock signals from the respective second level clock signals in accordance with their DLL functions and respective error signals. Respective groups of clock buffers of the Nth level subset are operable to produce the output clock signals of the respective clock distribution nodes from the respective third level clock signals in accordance with their DLL functions and respective error signals.
In accordance with one or more further aspects of the present invention, the semiconductor chip includes a global operative area defined by a plurality of regional areas, at least one sub-regional area within each regional area, and at least one local area within each sub-regional area; and at least one of the regional clock distribution nodes is disposed in each of the regional areas such that the respective outputs of an Nth level subset of clock buffers provides a regional clock signal to each of the regional areas.
The semiconductor chip preferably further includes a plurality of sub-regional clock distribution nodes disposed in each sub-regional area; and a plurality of RC-balanced clock signal paths coupled from each regional clock distribution node to the respective sub-regional clock distribution nodes of each sub-regional area such that respective sub-regional clock signals are provided at each regional clock distribution node.
In accordance with one or more further aspects of the invention, the semiconductor chip may further include a plurality of local clock distribution nodes arranged in respective distribution grids, at least one of the distribution grids being disposed in each local area; and a plurality of local clock buffers, respective ones of the local clock buffers receiving an associated one of the sub-regional clock signals from one of the sub-regional clock distribution nodes and producing a local clock signal on a respective one of the distribution grids, each local clock buffer including at least part of an active feedback function operable to cause the local clock signal at one of the local clock distribution nodes of the respective distribution grid to be substantially coincident with the associated sub-regional clock signal.
The semiconductor chip preferably further includes a phase lock loop operable to adjust a phase of the global source clock signal such that a phase difference between a system clock signal and one of the local clock signals is minimized.
In accordance with one or more further aspects of the present invention, a semiconductor chip includes: a plurality of regional clock distribution nodes located on the semiconductor chip; a plurality of clock buffers grouped into i-th levels, where i=1, 2 . . . N, each clock buffer being operable to output a respective i-th level clock signal from an associated (ixe2x88x921)th level clock signal in accordance with a delay lock loop (DLL) function, where the respective Nth level clock signals are coupled to the regional clock distribution nodes; and a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the i-th level clock signals of respective pairs of the regional clock distribution nodes, wherein the i-th level clock buffers adjust transitions of the respective i-th level clock signals in accordance with the DLL functions and the respective error signals.
In accordance with one or more further aspects of the present invention, a method of distributing clock signals to areas of a semiconductor chip includes: receiving a clock source signal, where the clock source signal is a 0xe2x88x92th level clock signal; producing respective i-th level clock signals from associated (ixe2x88x921)th level clock signals, where i=1, 2, . . . N; distributing the Nth level clock signals to respective regional clock distribution nodes located in regional areas of the semiconductor chip; producing respective error signals indicative of phase differences between respective pairs of the Nth level clock signals of the regional clock distribution nodes; adjusting instances at which the i-th level clock signals transition in accordance with the respective error signals such that the Nth level clock signals of the regional clock distribution nodes are substantially coincident.
The method preferably further includes dividing the semiconductor chip into a global operative area defined by a plurality of regional areas, at least one sub-regional area within each regional area, and at least one local area within each sub-regional area, wherein at least one of the regional clock distribution nodes is disposed in each of the regional areas such that a regional clock signal is provided to each of the regional areas.
The method may also include distributing the regional clock signals over a plurality of RC-balanced clock signal paths coupled from each regional clock distribution node to respective sub-regional clock distribution nodes, at least one sub-regional clock distribution node being disposed in each sub-regional area, such that respective sub-regional clock signals are provided at each sub-regional clock distribution node.
The method preferably further includes distributing the respective sub-regional clock signals over respective distribution grids, each coupled to a respective plurality of local clock distribution nodes, at least one of the distribution grids being disposed in each local area, such that respective local clock signals are provided at the respective pluralities of local clock distribution nodes; and adjusting instances at which the respective sub-regional clock signals transition in accordance with respective local DLL functions prior to distribution over the respective distribution grids such that the local clock signal at one of the local clock distribution nodes of the respective distribution grids is substantially coincident with the respective sub-regional clock signals.
The method may also include adjusting a phase of the global source clock signal such that a phase difference between a system clock signal and one of the local clock signals is minimized.
In accordance with one or more further aspects of the present invention, a method is contemplated of distributing clock signals to a plurality of regional clock distribution nodes located on a semiconductor chip using a plurality of clock buffers grouped into i-th levels, where i=1, 2 . . . N, each clock buffer being operable to output a respective i-th level clock signal from an associated (ixe2x88x921)th level clock signal in accordance with a delay lock loop (DLL) function, where the respective Nth level clock signals are coupled to the regional clock distribution nodes, and using a plurality of phase detectors, each being operable to produce a respective error signal indicative of phase differences between the clock signals of respective pairs of the regional clock distribution nodes, where the i-th level clock buffers adjust transitions of the respective i-th level clock signals in accordance with the DLL functions and the respective error signals.
The method includes: causing the respective i-th level clock buffers to neither substantially delay nor substantially advance the transitions of the respective i-th level clock signals; permitting the (Nxe2x88x92j)th level clock buffers to adjust the transitions of the respective (Nxe2x88x92i)th level clock signals, where j=0, 1, 2, . . . Nxe2x88x921; and repeating the previous step for each level such that the Nth level clock signals of the regional clock distribution nodes are substantially coincident with one another and a 0th level clock signal.
Other features and advantages of the present invention will become apparent in light of the description herein taken in combination with the accompanying drawings.